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Senior Principal ASIC Design Engineer (Hybrid) - San Jose California
Company: Disability Solutions Location: San Jose, California
Posted On: 05/08/2024
Job Description You don't see it, but it's there. Our employees work on the world's most advanced electronics - from saving emissions in the City of Lights to powering the Mars Rover to protecting the F-35 fighter jet. At Electronic Systems, you'll be among the brightest minds, working on the aerospace and defense industry's most difficult problems. Drawing strength from our differences, we're innovating for the future. And you can, too. Our flexible work environment provides you a chance to change the world without giving up your personal life. We put our customers first - exemplified by our missions: "We Protect Those Who Protect Us--" and "We Innovate For Those Who Move The World---." Sound like a team you want to be a part of? Come build your career with BAE Systems.We are seeking a very senior level engineer to: - Design and RTL coding of high-speed digital circuits on ASIC/FPGAs from concept to production.
- Defining detailed test plan and implementing Verilog simulation testcases to verify design functionality.
- Debug product, test and resolve design issues on hardware platforms
- Define hardware and firmware interfaces, protocols for circuits.
- Integration of IP cores Buses, Controllers, PHYs, etc with other logic within ASIC/FPGA
- Coordinate interoperability of digital modules with embedded software
- Build verification environment using SV/UVM methodology
- Build reusable bus functional models, monitors, checkers and scoreboards
- Solid understanding of verification methodologies, especially UVM(SystemVerilog), including:
- Test planning
- Testbench creation
- Code and Functional coverage
- Directed and random stimulus generation
- Assertions
- Regression triageBecause this role involves a combination of collaborative/in-person and independent work, it will take the form of a hybrid work format, with time split between working onsite and remotely.Required Education, Experience, & Skills
- Proficient in Verilog language for ASIC/FPGA design
- Knowledge of ASIC and FPGA design flows is highly desirable
- Knowledge simulation and verification methodologies (VCS simulator, UVM)
- Proficient in ASIC/FPGA timing closure/area optimization techniques
- Hands on Experience with bring-up of ASIC/FPGA designs
- Excellent organization and communication skills for interacting between different design groups
- Proficiency in C/C++ and scripting languages is a plus.Preferred Education, Experience, & Skills
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