|
ASIC Verification Engineer - San Jose California
Company: Cisco Systems, Inc. Location: San Jose, California
Posted On: 04/26/2024
Who We Are The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. With -2,100 employees across 16 countries, we design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry. Who You'll Work With You will be in the Silicon One development organization as an ASIC design verification engineer in San Jose, CA. You collaborate closely with verification engineers, designers, hardware and cross functional teams to verify the ASIC in simulation, in emulation and during ASIC bring up. What You'll Do - Maintaining existing DV environments and enhancing them
- Construct testbench including scoreboard, agents, sequencers, and monitors for new blocks
- Write test plan, develop testcases, debug regression failures and drive to module verification closure
- Ensuring complete verification coverage through implementation and review of code and functional coverage Who You Are
- You are an ASIC Design Verification Engineer with 5+ years of related work experience with a Bachelor's or Master degree.
- You will have an ASIC design verification background with hands-on experience in RTL verification and in-depth knowledge of SoC development cycle and the best industry practices, from specification through tape-out and lab validation, and a proven track record of success in high-performance/high-volume semiconductor markets. Minimum qualifications
- Hands-on and deep understanding of System Verilog and UVM methodology
- Experience in verifying complex blocks, clusters and top level for SoC
- Can build testbenches from scratch, hands on experience with System Verilog constraints, structures and classes.
- Ability to debug issues independently
- Proficient in functional coverage and constrained random DV environments.
- Scripting skills: Perl and/or Python scripting
- Strong domain experience in one or more protocols in a plus - PCIe, CXL, Ethernet, AHB/AXI, DDR, MMU.
- Experience with Veloce/HAPS is a plus
- Formal verification (iev/vc formal) knowledge is a plusPreferred skils
|
|