Senior ASIC Design Engineer - San Jose California

Company: InnoPhase IoT
Location: San Jose, California
Posted On: 04/19/2024

Job Description:
Join Innophase IoT as a Senior ASIC Design Engineer and be contribute to the development ofLow-power WiFi, BT/BLE RTL design, and implementation. You will be involved in the designdevelopment cycle, which includes participating in high-level product specifications, RTLdevelopment, working closely with RTL design and verification engineers.
Your specific responsibilities may include but are not limited to the following:

• Run synthesis, STA setup, and logic equivalency checks.
  
• Run Linting, Clock-domain-crossing, Reset-domain-crossing checks.
  
• Help run scripts to generate memories, memBIST, and DFT logic
  
• Contribute to micro-architecture, and develop SystemVerilog RTL with established guidelines tomeet size, timing, and power target.
  
• Develop, and refine scripting and analysis tools to automate and enhance ASIC developmentflow
  
• Work closely with RTL, and Physical Design teams at various stages of product development
  
  Required Qualifications:
  
  
  
  • Eagerness to learn, collaborate, and enjoy debugging and problem solving in a teamenvironment.
    
  • Experience with Python, Perl, Tcl, and shell scripts
    
  • 4+ years of experience in RTL design using Verilog, SystemVerilog
    
  • Experience in synthesis, timing closure for FPGA and/or ASICs
    
  • Experience with front-end design and integration tasks including lint, CDC, synthesis, and developing timing ECOs.
    
  • BSEE or MSEE, with experience in ASIC development and/or FPGA prototyping
    
  • Ability to work independently, and proactively identify and resolve issues.
    
  • Experience with Incisive/Excellium/VCS, Verdi, Jasper/Spyglass or equivalent tools
    
    Preferred Qualifications:
    
    
    
    • Experience in Low Power design development (UPF/CPF), involving multiple power, andvoltage domains.
      
    • Expertise in working w/ APB/AHB/AXI bus protocols.
      
    • Understanding of wireless standards, such as IEEE 802.11, 802.15, Bluetooth is a plus, but not required.
      
    • Experience with lab debug, multi-team, multi-site working environment is a strong plus.
      
    • Experience using PowerArtist/Joules and providing actionable feedback into design.
      
      
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